|Department of Computer Science |
Course: CS 3725
A cache miss on an instruction fetch requires that the processor ``stall'' or wait until the instruction is available from main memory.
A cache miss on a data read may be less serious; instructions can, in principle, continue execution until the data to be fetched is actually required. In practice, data is used almost immediately after it is fetched.
A cache miss on a data word write may be even less serious; if the write is buffered, the processor can continue until the write buffer is full. (Often the write buffer is only one word deep.)
If we know the miss rate for reads in a cache memory, we can calculate the number of read-stall cycles as follows:
For writes, the expression is similar, except that the effect of the write buffer must be added in:
In many cache memory systems, the penalties are the same for a cache read or write. Here we can use a single miss rate, and miss penalty:
Assume a cache ``miss rate'' of 5%, (a ``hit rate'' of 95%) with cache memory of 20ns cycle time, and main memory of 150ns cycle time. We can calculate the average cycle time as
The following table shows the effective memory cycle time as a function of cache hit rate for the system in the above example:
|Cache hit %||Effective cycle time (ns)|
Note that there is a substantial performance penalty for a high cache miss rate.