Performance modeling of multithreaded distributed memory architectures

Zuberek, W.M.

in "Hardware Design and Petri Nets", A. Yakovlev, L. Gomes, L. Lavagno (eds.), pp.311-331, Kluwer Academic Publ. 2000.

Abstract:

In multithreaded distributed memory architectures, long-latency memory operations and synchronization delays are tolerated by suspending the execution of the current thread and switching to another thread, which is executed concurrently with the long-latency operation of the suspended thread. Timed Petri nets are used to model several multithreaded architectures at the instruction and thread levels. Model evaluation results are presented to illustrate the influence of different model parameters on the performance of the system.

Keywords:

Multithreaded architectures, distributed-memory architectures, performance modeling, timed Petri nets, discrete-event simulation.

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