Performance analysis of enhanced fine-grain multithreaded distributed-memory systems

Zuberek, W.M.

Proc. IEEE Conf. on Systems, Man, and Cybernetics; Tucson, AZ, 7-10 October 2001, pp.1101-1106.

Abstract:

In fine-grain multithreading, the thread changes in each processor cycle, consecutive instructions are thus issued from different threads, and no data dependencies stall the pipeline. Enhanced fine-grain multithreading maintains a number of additional threads which are used to replace an active thread when it initiates a long-latency operation. Performance improvements due to enhanced multithreading are studied by analyzing a timed Petri net model of a fine-grain multithreaded architecture at the instruction execution level.

Keywords:

Fine-grain multithreading, distributed-memory architectures, timed Petri nets, performance analysis, discrete-event simulation.

References:

• Byrd, G.T., Holliday, M.A., "Multithreaded processor architecture"; IEEE Spectrum, vol.32, no.8, pp.38-46, 1995.
• Dennis, J.B., Gao, G.R., "Multithreaded architectures: principles, projects, and issues"; in Multithreaded Computer Architecture: A Summary of the State of the Art", pp.1-72, Kluwer Academic 1994.
• Govindarajan, R., Nemawarkar, S.S., LeNir, P., "Design and performance evaluation of a multithreaded architecture"; Proc. First IEEE Symp. on High-Performance Computer Architecture, Raleigh, NC, pp.298-307, 1995.
• Govindarajan, R., Suciu, F., Zuberek, W.M., "Timed Petri net models of multithreaded multiprocessor architectures"; Proc. 7-th Int. Workshop on Petri Nets and Performance Models (PNPM'97), St. Malo, France, pp.153-162, 1997.
• Hamilton, S., "Taking Moore's law into the next century"; IEEE Computer Magazine, vol.32, no.1, pp.43-48, 1999.
• Murata, T., "Petri nets: properties, analysis and applications"; Proceedings of IEEE, vol.77, no.4, pp.541-580, 1989.
• Patterson, D.A., Hennessy, J.L., ``Computer Architecture - A Qualitative Approach; Morgan Kaufman 1996.
• Reisig, W., Petri Nets - An Introduction (EATCS Monographs on Theoretical Computer Science 4); Springer-Verlag 1995.
• Smith, B.J., "Architecture and applications of the HEP multiprocessor computer system"; Proc. SPIE - Real-Time Signal Processing IV, vol. 298, pp. 241-248, 1981.
• Sohi, G.S., "Microprocessors - 10 years back, 10 years ahead"; in Informatics: 10 Years Back, 10 Years Ahead (Lecture Notes in Computer Science 2000), pp.209-218, 2001.
• Wang, J., Timed Petri Nets; Kluwer Academic Publ. 1998.
• Zuberek, W.M., "Timed Petri nets - definitions, properties and applications"; Microelectronics and Reliability (Special Issue on Petri Nets and Related Graph Models), vol.31, no.4, pp.627-644, 1991.
• Zuberek, W.M., "Performance comparison of fine-grain and block multithreaded architectures"; Proc. High Performance Computing Symposium 2000, Washington, DC, pp.383-388, 2000.

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