Performance balancing of fine-grain multithreaded distributed-memory multiprocessors

Zuberek, W.M.

Proc. High Performance Computing Symposium (HPC'02); San Diego, CA, 14-18 April 2002, pp.129-134.

Abstract:

Instruction-level multithreading is an architectural approach to tolerating long-latency memory accesses and synchronization delays in distributed-memory systems. If the system is unbalanced, one of its components (such as memory or the interconnecting network) becomes the bottleneck which limits the performance of all other components. The paper studies the criteria for a fine-grain multithreaded system to be balanced and illustrates the considerations by performance results obtained for a simple 16-processor system.

Keywords:

Distributed-memory architectures, fine-grain multithreading, timed Petri nets, performance analysis, discrete-event simulation.

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