Approximate performance evaluation of multithreaded distributed memory architectures

Zuberek, W.M.

Proc. 15-th Performance Engineering Workshop, Bristol, UK, 22-23 July 1999, pp.81-92.

Abstract:

The long-latency memory accesses and unpredictable synchronization delays in multithreaded distributed memory architectures are tolerated by context switching, i.e., by suspending the current thread and switching the processor to another thread waiting for execution. Simple queueing models of multithreaded processors and their interconnecting network are used for finding approximate performance measures for the boundaries of the space of model parameters. These approximate measures are compared with performance results obtained by simulation of a detailed model of the analyzed architecture.

Keywords:

Instruction-level multithreading, distributed-memory architectures, queueing models, performance estimation.

References:

• Agarwal, A., "Performance tradeoffs in multithreaded processors"; IEEE Trans. on Parallel and Distributed Systems; vol.3, no.5, pp.525-539, 1992.
• Alkalaj, L., Boppana, R.V., "Performance of a multithreaded execution in a shared-memory multiprocessor"; Proc. 3-rd Annual IEEE Symp. on Parallel and Distributed Processing, Dallas, TX, pp.330-333, 1991.
• Alverson, R., Callahan, D., Cummings, D., Koblenz, B., Posterfield, A., Smith, B., "The Tera computer system"; Proc. Int. Conf. on Supercomputing, Amsterdam, The Netherlands, pp.1-6, 1990.
• Boothe, B. and Ranade, A., "Improved multithreading techniques for hiding communication latency in multiprocessors"; Proc. 19-th Annual Int. Symp. on Computer Architecture, pp.214-223, 1992.
• Byrd, G.T., Holliday, M.A., "Multithreaded processor architecture"; IEEE Spectrum, vol.32, no.8, pp.38-46, 1995.
• Dennis, J.B., Gao, G.R., "Multithreaded architectures: principles, projects, and issues"; in Multithreaded Computer Architecture: A Summary of the State of the Art, Kluwer Academic Publ., pp.1-72, 1994.
• Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L., Tullsen, D.M., "Simultaneous multithreading: a platform for next-generation processors"; IEEE Micro, vol.17, no.5, pp.12-19, 1997.
• Hilly, S., Seznec, A., "Out-of-order execution may not be cost-effective on processors featuring simultaneous multithreading"; Proc. 5-th Int. Symp. on High Performance Computer Architecture (HPCA'99), Orlando, FL, pp.64-67, 1999.
• Keckler, S.W., Dally, W.J., "Processor coupling: integration of compile-time and run-time scheduling for parallelism"; Proc. 19-th Annual Int. Symp. on Computer Architecture, pp.202-213, 1992.
• Laudon, J., Gupta, A., Horowitz, M., "Interleaving: a multithreaded technique targeting multiprocessors and workstations"; Proc. Symp. on Architectural Support for Programming Languages and Operating Systems (ASPLOS'94), pp.308-318, 1994.
• Nemawarkar, S.S., Govindarajan, R., Gao, G.R., Agarwal, V.K., "Analysis of multithreaded multiprocessors with distributed shared memory"; Micronet Report, Department of Electrical Engineering, McGill University, Montreal, Canada H3A 2A7, 1993.
• Saavedra-Bareera, R.H., Culler, D.E., von Eicken, T., "Analysis of multithreaded architectures for parallel computing"; Proc. 2-nd Annual Symp. on Parallel Algorithms and Architectures, Crete, Greece, 1990.
• Serano, M.J., "Performance estimation in a simultaneous multithreading processor"; Proc. 4-th Int. Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS-96), San Jose, CA, pp.97-101, 1996.
• Smith, B.J., "Architecture and applications of the HEP multiprocessor computer system"; Proc. SPIE - Real-Time Signal Processing IV, vol. 298, pp. 241-248, San Diego, CA, 1981.
• Zuberek, W.M., Govindarajan, R., "Performance balancing in multithreaded multiprocessor architectures"; Proc. 4-th Australasian Conf. on Parallel and Real-Time Systems (PART'97), Newcastle, Australia, pp.15-26, 1997.
• Zuberek, W.M., Govindarajan, R., "Performance bounds for distributed memory multithreaded architectures"; Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'98), San Diego, CA, pp.232-237, 1998.

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